參數(shù)資料
型號: MSC1200Y3PFBT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 63/93頁
文件大?。?/td> 1093K
代理商: MSC1200Y3PFBT
MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
66
Program Status Word (PSW)
7
6
5
4
3
2
1
0
Reset Value
SFR D0h
CY
AC
F0
RS1
RS0
OV
F1
P
00h
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during
bit 7
subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
AC
Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or
bit 6
a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0
Register Bank Select 10. These bits select which register bank is addressed during register accesses.
bits 43
RS1
RS0
REGISTER BANK
ADDRESS
0
00h 07h
0
1
08h 0Fh
1
0
2
10h 17h
1
3
18h 1Fh
OV
Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction),
bit 2
or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to
bit 0
‘0’ on even parity.
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