參數(shù)資料
型號(hào)： MSC1200Y3PFBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 19/93頁(yè)
文件大?。?/td> 1093K
代理商： MSC1200Y3PFBT
MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
26
VOLTAGE REFERENCE
The MSC120x can use either an internal or external
voltage reference. The voltage reference selection is
controlled via ADC Control Register 0 (ADCON0, SFR
DCh). The default power-up configuration for the voltage
reference is 2.5V internal.
The internal voltage reference can be selected as either
1.25V or 2.5V. The analog power supply (AVDD) must be
within the specified range for the selected internal voltage
reference. The valid ranges are: VREF = 2.5 internal
(AVDD = 3.3V to 5.25V) and VREF = 1.25 internal
(AVDD = 2.7V to 5.25V). If the internal VREF is selected,
then AGND must be connected to REFIN. The
REFOUT/REFIN+ pin should also have a 0.1
F capacitor
connected to AGND as close as possible to the pin. If the
internal VREF is not used, then VREF should be disabled in
ADCON0.
If the external voltage reference is selected, it can be used
as either a single-ended input or differential input, for
ratiometric measures. When using an external reference,
it is important to note that the input current will increase for
VREF with higher PGA settings and with a higher modulator
frequency. The external voltage reference can be used
over
the
input
range
specified
in
the
Electrical
Characteristics section.
IDAC
The 8-bit IDAC in the MSC120x provides a current source
that can be used for ratiometric measurements. The IDAC
operates from its own voltage reference and is not
dependent on the ADC voltage reference. The full-scale
output current of the IDAC is approximately 1mA (within
the compliance voltage range). The equation for the IDAC
output current is:
IDAC
OUT mA [ IDAC @ 3.9mA (at 25°C)
The IDAC output voltage cannot exceed the compliance
voltage of AVDD 1.5V.
RESET
The MSC120x can be reset from the following sources:
D Power-on reset
D External reset
D Software reset
D Watchdog timer reset
D Brownout reset
An external reset is accomplished by taking the RST pin
high for two tOSC periods, followed by taking the RST pin
low. A software reset is accomplished through the System
Reset register (SRTST, 0F7h). A watchdog timer reset is
enabled and controlled through Hardware Configuration
Register 0 (HCR0) and the Watchdog Timer register
(WDTCON, 0FFh). A brownout reset is enabled through
Hardware Configuration Register 1 (HCR1). Power-on
reset and external reset complete after 217 clock cycles,
using the internal oscillator in low-frequency mode.
Brownout reset, watchdog timer reset, and software reset
complete after 215 clock cycles, using the active clock
source.
All sources of reset cause the digital pins to be pulled high
from the initiation of the reset procedure. For an external
reset, taking the RST pin high stops device operation
(crystal oscillation, internal oscillator, or PLL circuit
operation) and causes all digital pins to be pulled high from
that point. Taking the RST pin low initiates the reset
procedure.
A recommended external reset circuit is shown in
Figure 12. The serial 10k
resistor is recommended for
any external reset circuit configuration. For proper
execution of the reset procedure, it is necessary to keep
the AVDD supply above 2.0V during the reset procedure.
10k
4RST
MSC120x
0.1
F
1M
DV
DD
Figure 12. Typical Reset Circuit
Note that pin P1.0/PROG defines operation of the device
after reset. If P1.0/PROG is not connected or pulled high
during reset, the device will enter User Application mode
(UAM). If P1.0/PROG is pulled low during reset, the device
will enter Serial Flash Programming mode (SFPM). Refer
to the Electrical
Characteristics section for timing
information.
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