參數(shù)資料
型號： MR80C52XXX-25SHXXX:R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁數(shù)： 151/176頁
文件大?。?/td> 4226K
76
8126F–AVR–05/12
ATtiny13A
11.9.7
TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bits 7:4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
Bit 3 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
Bit 2 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM0[2:0] bit setting. Refer to Table 11-8, “Wave-
Bit
7
65432
10
–
OCF0B
OCF0A
TOV0
–TIFR0
Read/Write
R
R/W
R
Initial Value
0
00000
00
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