參數(shù)資料
型號(hào)： MR80C52XXX-25SHXXX:R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁數(shù)： 120/176頁
文件大?。?/td> 4226K
48
8126F–AVR–05/12
ATtiny13A
9.3.3
GIFR – General Interrupt Flag Register
Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
9.3.4
PCMSK – Pin Change Mask Register
Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0
Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[5:0] is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[5:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
76543210
–
INTF0
PCIF
–––––
GIFR
Read/Write
R
R/W
RRRRR
Initial Value
00000000
Bit
76543210
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
PCMSK
Read/Write
R
R/W
Initial Value
00000000
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