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| 型號(hào)： | MR80C52CXXX-12/883:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 83/125頁(yè) |
| 文件大?。?/td> | 6456K |
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264
7707F–AVR–11/10
AT90USB82/162
1.)The sum of all IOL, for ports B0-B7, C0-C7, D0-D7 should not exceed 150 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady
state conditions (non-transient), the following must be observed:
1.)The sum of all IOL, for ports B0-B7, C0-C7, D0-D7 should not exceed 150 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcon-
trollers manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon
6. Values with “Power Reduction Register 1 - PRR1” disabled (0x00).
7. As specified in the USB Electrical chapter, the D+/D- pads can withstand voltages down to -1V applied through a 39
Ω resis-
tor (in series with the external 22
Ω resistor).
8. All IOs Except XTAL1, MOSI, MISO, PS2 and Reset pins
26.3
External Clock Drive Waveforms
Figure 26-1. External Clock Drive Waveforms
26.4
External Clock Drive
Note:
All DC Characteristics contained in this datasheet are based on simulation and characterization of
other AVR microcontrollers manufactured in the same process technology. These values are pre-
liminary values representing design targets, and will be updated after characterization of actual
silicon.
VIL1
VIH1
Table 26-1.
External Clock Drive
Symbol
Parameter
VCC=2.7-5.5V
VCC=4.5-5.5V
Units
Min.
Max.
Min.
Max.
1/tCLCL
Oscillator
Frequency
08
0
16
MHz
tCLCL
Clock Period
125
62.5
ns
tCHCX
High Time
50
25
ns
tCLCX
Low Time
50
25
ns
tCLCH
Rise Time
1.6
0.5
μs
tCHCL
Fall Time
1.6
0.5
μs
Δt
CLCL
Change in period
from one clock
cycle to the next
22
%
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