- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > MR80C52CXXX-12/883:D (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 PDF資料下載
參數(shù)資料
| 型號(hào)： | MR80C52CXXX-12/883:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 61/125頁 |
| 文件大?。?/td> | 6456K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁
228
32117D–AVR-01/12
AT32UC3C
14.4
I/O Lines Description
14.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
14.5.1
I/O Lines
Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an
external source the source pin must be configured as an input pin by the I/O Controller. It is also
possible to trigger a peripheral event by driving these pins from registers in the I/O Controller, or
another peripheral output connected to the same pin.
14.5.2
Power Management
If the CPU enters a sleep mode that disables clocks used by the PEVC, the PEVC will stop func-
tioning and resume operation after the system wakes up from sleep mode. Peripheral events do
not require CPU intervention, and are therefore available in sleep modes where the CPU sleeps.
14.5.3
Clocks
The PEVC has two bus clocks connected: One Peripheral Bus clock (CLK_PEVC) and the sys-
tem RC oscillator clock (CLK_RCSYS). These clocks are generated by the Power Manager.
Both clocks are enabled at reset, and can be disabled by writing to the Power Manager.
CLK_RCSYS is used for glitch filtering.
14.5.4
Interrupts
PEVC can generate an interrupt request in case of trigger generation or trigger overrun. The
PEVC interrupt request lines are connected to the interrupt controller. Using the PEVC interrupts
requires the interrupt controller to be programmed first.
14.5.5
Debug Operation
PEVC is frozen during debug operation, unless the Run In Debug bit in the Development Control
Register is set and the bit corresponding to the PEVC is set in the Peripheral Debug Register
(PDBG). Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Man-
ual, and the OCD Module Configuration section, for details.
Table 14-1.
I/O Lines Description
Pin Name
Pin Description
Type
PAD_EVT[n]
External Event Inputs
Input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC80C52EXXX-12SC | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52TXXX-16SHXXX:D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C52CXXX-12SCR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52XXX-25 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。