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| 型號： | MPM21CUB500A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 500 MHz, MICROPROCESSOR, XMA |
| 封裝： | MMC-2 |
| 文件頁數(shù)： | 4/64頁 |
| 文件大?。?/td> | 826K |
| 代理商： | MPM21CUB500A |
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Celeron
Processor Mobile Module MMC-2
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
6
Datasheet
243357-005
3.1.3
AGP Signals
Table 3 provides descriptions of the AGP interface signals.
Table 3.
AGP Signal Descriptions
Name
Type
Voltage
Description
GAD[31:]
I/O
AGP
V_3
AGP Address/Data: The standard AGP address and data lines. This
bus functions in the same way as the PCI AD[31:0] bus. The address
is driven with FRAME# assertion, and data is driven or received in
following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable: This bus carries the command
information during AGP cycles when PIPE# is used. During an AGP
write, this bus contains byte enable information. The command is
driven with FRAME# assertion and byte enables corresponding to
supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame: Not used during AGP transactions. Remains
deasserted by an internal pullup resistor. Assertion indicates the
address phase of a PCI transfer. Negation indicates that the cycle
initiator desires one more data transfer.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select: This signal provides the same function as PCI
DEVSEL#. It is not used during AGP transactions. The 82443BX Host
Bridge system controller drives this signal when a PCI initiator is
attempting to access DRAM. DEVSEL# is asserted at medium
decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready: Indicates the AGP-compliant target is ready to
provide all write data for the current transaction. Asserted when the
initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready: Indicates the AGP-compliant master is ready to
provide all write data for the current transaction. Asserted when the
target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop: This signal provides the same function as PCI STOP#. It
is not used during AGP transactions. Asserted by the target to
request the master to stop the current transaction.
GREQ#
I
AGP
V_3
AGP Request: AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant: This signal provides the same function as on PCI.
Additional information is provided on the ST[2:0] bus. PCI Grant:
Permission is given to the master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity: A single parity bit is provided over GAD[31:0] and GC/
BE[3:0]. This signal is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request: Asserted by the current master to indicate a full
width address that is to be queued by the target. The master queues
one request each rising clock edge while PIPE# is asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address: This bus provides an additional conduit to pass
address and commands to the 82443BX Host Bridge System
Controller from the AGP master.
RBF#
I
AGP
V_3
Read Buffer Full: RBF# indicates if the master is ready to accept
previously requested, low-priority read data.
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