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參數(shù)資料
| 型號： | MPE603RRX300LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 418K |
| 代理商： | MPE603RRX300LX |
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2
EC603e Microprocessor Hardware Specifications (PID7t), Rev. 2.0
MOTOROLA
This document contains the following topics:
Topic
Page
Section 1.1, Overview
2
Section 1.2, Features
3
Section 1.3, General Parameters
4
Section 1.4, Electrical and Thermal Characteristics
4
Section 1.5, Pin Assignments
15
Section 1.6, Pinout Listings
16
Section 1.7, Package Descriptions
18
Section 1.8, System Design Information
20
Section 1.9, Ordering Information
27
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/PowerPC/.
1.1 Overview
This section describes the features of the PID7t and describes briey how those units interact.
The PID7t is a low-power implementation of the PowerPC microprocessor family of reduced instruction set
computing (RISC) microprocessors. The PID7t implements the 32-bit portion of the PowerPC architecture
specication, which provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits. For 64-
bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit
addressing, and other features required to complete the 64-bit architecture.
The PID7t provides four software controllable power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the PID7t to
automatically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The PID7t is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the PID7t makes completion
appear sequential.
The PID7t integrates four execution unitsan integer unit (IU), a branch processing unit (BPU), a load/
store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and
the use of simple instructions with rapid execution times yield high efciency and throughput for PID7t-
based systems. Most integer instructions execute in one clock cycle.
The PID7t provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches
for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The PID7t also
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The PID7t has a selectable 32- or 64-bit data bus and a 32-bit address bus. The PID7t interface protocol
allows multiple masters to compete for system resources through a central external arbiter. The PID7t
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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