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參數(shù)資料
| 型號： | MPE603PRX200LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 34/36頁 |
| 文件大?。?/td> | 201K |
| 代理商： | MPE603PRX200LX |
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PRELIMINAR
Y
MOTOROLA
EC603e Microprocessor Hardware Specifications (PID7v)
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the PID7v. These specications are for 166 and
200 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK)
frequency and the settings of the PLL_CFG[0–3] signals. All timings are specied respective to the rising
edge of SYSCLK. PLL_CFG signals should be set prior to power up and not altered afterwards.
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1. After fabrication, parts are sorted
by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specications” and tested
for conformance to the AC specications for that frequency. Parts are sold by maximum processor core
frequency; see Section 1.9, “Ordering Information.”
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C
Num
Characteristic
166 MHz
200 MHz
Unit
Notes
Min
Max
Min
Max
Processor frequency
125
167
125
200
MHz
1
VCO frequency
250
333
250
400
MHz
1
SYSCLK frequency
25
66.67
25
66.67
MHz
1
SYSCLK cycle time
15
40.0
15
40.0
ns
2,3
SYSCLK rise and fall time
—
2.0
—
2.0
ns
2
4
SYSCLK duty cycle measured at 1.4 V
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
±150
—
±150
ps
4
PID7v internal PLL-relock time
—
100
—
100
s
3,5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in
Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term
combined) must be under
±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during
the power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
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