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參數(shù)資料
| 型號： | MPE603PRX200LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 201K |
| 代理商： | MPE603PRX200LX |
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PRELIMINAR
Y
28
EC603e Microprocessor Hardware Specifications (PID7v)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Notes:
1. Junction-to-ambient thermal resistance is based on measurements on single-sided printed circuit
boards per SEMI (Semiconductor Equipment and Materials International) G38-87 in natural
convection.
2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-
88 with the exception that the cold plate temperature is used for the case temperature.
The vendors who supply heat sinks are Aavid Engineering, IERC, Thermalloy, and Wakeeld Engineering.
Contact information for these vendors follows:
Thermalloy
214-243-4321
2021 W. Valley View Lane
P.O. Box 810839
Dallas, TX 75731
International Electronic Research Corporation (IERC)
818-842-7277
135 W. Magnolia Blvd.
Burbank, CA 91502
Aavid Engineering
603-528-3400
One Kool Path
Laconic, NH 03247-0440
Wakeeld Engineering
617-245-5900
60 Audubon Rd.
Wakeeld, MA 01880
Ultimately, the nal selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.8.6.2 Motorola CBGA Package
The data found in this section concerns PID7v’s packaged in the 255-lead 21 mm multi-layer ceramic
(MLC), ceramic BGA package. Data is shown for two cases, the exposed-die case (no heat sink) and using
the Thermalloy 2338-pin n heat sink.
1.8.6.2.1 Thermal Characteristics
The internal thermal resistance for this package is negligible due to the exposed die design. A heat sink is
attached directly to the silicon die surface only when external thermal enhancement is necessary.
Additionally, the CBGA package offers an exceptional thermal connection to the card and power planes.
Heat generated at the chip is consumed through the package, the heat sink (when used) and the card. The
parallel heat ow paths result in the lowest overall thermal resistance as well as offer signicantly better
power consumption capability when a heat sink is not used.
1.8.6.2.2 Thermal Management Example
The following example is based on a typical desktop conguration using a solder-bump 21 mm CBGA
package. The heat sink shown is the Thermalloy pinn heat sink #2338 attached directly to the exposed die
with a two-stage thermally conductive epoxy.
The calculations are performed exactly as shown in the previous section.
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