參數(shù)資料
型號(hào): MPC9990
廠商: Motorola, Inc.
英文描述: Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器)
中文描述: 低電壓PLL時(shí)鐘驅(qū)動(dòng)器(低壓鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器)
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 143K
代理商: MPC9990
MPC9990
MOTOROLA
6
AC CHARACTERISTICS
(VCCI = VCCA = 3.3V
±
5%, VCCO = 1.7 to 2.1V, TA = 0
°
to 70
°
C)1
0
°
C
25
°
C
70
°
C
Symbol
Characteristic
Input Frequency2
VCO Frequency3
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Condition
fIN
fVCO
VPP4
150
300
150
300
150
300
MHz
fVCO < 2 GHz
2000
2000
2000
MHz
Minimum Input Swing
(VDIF, IN)
0.4
1.75
0.4
1.75
0.4
1.74
V
Differential
HSTL inputs
VDIF,
OUT
Minimum Output Swing
0.6
0.6
0.6
V
Differential
HSTL outputs
VX
Differential output
crosspoint voltage
0.68
0.9
0.68
0.9
0.68
0.9
V
Differential
HSTL outputs
tSkew
Differential output skew
within device
50
50
50
ps
Differential
HSTL outputs
tSkew
Differential output skew
device–to–device
200
200
200
ps
Differential
HSTL outputs
tJitter
tLock
1. Refer to ”HSTL Output Termination and AC Test Reference” on page 6 for AC test conditions.
2. The input frequency for the output configurations CLK * 7 / 8 and CLK * 8 / 9 are limited to fVCO < 2000 MHz. The CLK * 7 / 8 configuration limits
fIN to 285 MHz, the CLK * 8 / 9 configuration limits fIN to 250 MHz.
3. fVCO specification is pending device characterization.
4. VPP specifies the minimum input differential voltage required for switching.
5. Jitter specification is pending device characterization. Maximum number represents design target. Cycle–to–cycle jitter is the period variation
between adjacent clock cycles.
Cycle–to–cycle jitter5
75
75
75
ps
PLL lock time
10
10
10
ms
Figure 6. HSTL Output Termination and AC Test Reference
MPC9990 Output
Z = 50
RT = 50
VTT = GND
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