- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371135 > MPC993 (Motorola, Inc.) Dynamic Switch PLL Clock Driver(動(dòng)態(tài)開(kāi)關(guān)PLL時(shí)鐘驅(qū)動(dòng)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC993 |
| 廠(chǎng)商： | Motorola, Inc. |
| 英文描述： | Dynamic Switch PLL Clock Driver(動(dòng)態(tài)開(kāi)關(guān)PLL時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 動(dòng)態(tài)開(kāi)關(guān)PLL時(shí)鐘驅(qū)動(dòng)器（動(dòng)態(tài)開(kāi)關(guān)鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | MPC993 |
MPC993
3
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3.3V PECL AC Characteristics
(TA = 0
°
C to 85
°
C)
Symbol
Parameter
Min
Typ
Max
Unit
fVCO
tpwi
tpd
PLL VCO Lock Range
TBD (Note 5.)
MHz
25
75
%
Propagation Delay (Note 1.)
CLKn to Q (Bypass)
CLKn to Q (Locked (Note 2.))
X–500
Y–150
2000
0
X+500
Y+150
ps
tr/tf
tskew
Output Rise/Fall Time
200
800
ps
Output Skew
Within Bank
All Outputs
50
100
ps
pe
Maximum Phase Error Deviation
TBD (Note 3.)
TBD (Note 4.)
ps
per/cycle
Rate of Change of Periods
75MHz Output (Note 3.)
150MHz Output (Note 3.)
75MHz Output (Note 4.)
150MHz Output (Note 4.)
20
10
TBD
TBD
ps
tpw
tjitter
tlock
Output Duty Cycle
45
55
%
Cycle–to–Cycle Jitter
50
ps
Maximum PLL Lock Time
10
ms
1. These values represent simulation results. Final values will be determined from silicon measurements and may be adjusted slightly.
2. Static phase offset between the selected reference clock and the feedback signal.
3. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over
the clock switch excursion. (See Applications Information section on page 4 for more detail)
4. Specification holds for a clock switch between two signals no greater than
±
π
out of phase. Delta period change per cycle is averaged over the
clock switch excursion.
5. The PLL will be unstable using a
÷
2 output as the feedback. Either one of the
÷
4 outputs (Qa0 or Qa1) should be used as the feedback signal.
PIN DESCRIPTIONS
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Qa0:1, Qa0:1
LVPECL Output
Differential 1x output pairs
Qb0:2, Qb0:2
LVPECL Output
Differential 2x output pairs
Inp0bad
LVCMOS Output
Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output
Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
LVCMOS Output
‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected
Alarm_Reset
LVCMOS Input
‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one–shotted”
(50k
pullup)
Sel_Clk
LVCMOS Input
‘0’ selects CLK0, ‘1’ selects CLK1 (50k
pulldown)
Manual_Override
LVCMOS Input
‘1’ disables internal clock switch circuitry (50k
pulldown)
PLL_En
LVCMOS Input
‘0’ bypasses selected input reference around the phase–locked loop (50k
pullup)
MR
LVCMOS Input
‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k
pullup)
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL ground
GND
Power Supply
Digital ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9990 | Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器) |
| MPF102 | JFET VHF Amplifier |
| MPF102 | JFET VHF Amplifier |
| MPF102 | N-Channel RF Amplifier |
| MPF4392 | JFETs Switching |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。