- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄26839 > MPC96877VKR2 (FREESCALE SEMICONDUCTOR INC) 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52 |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大小： | 395K |
| 代理商： | MPC96877VKR2 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC96877
1. There are two different terminations that are used with the following tests. The loadboard in Figure 3 is used to measure the input and
output differential-pair cross voltage only. The loadboard in Figure 4 is used to measure all other tests. For consistency, use 50 ohms equal
length cables with SMA connectors.
2. Static Phase offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
4. The Output Slew Rate is determined from the IBIS model into the load shown in Figure 2. It is measured single ended.
5. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with
these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the reg-
istered DDR2 DIMM application.
6. Static Phase offset does not include Jitter.
7. VOX is specified at DDR DRAM clock input or test load.
Table 7. Switching Characteristics over Recommended Free-Air Operating Temperature Range Unless Otherwise Noted
(see Notes)
Description
Parameter
Diagram
AVDD, VDDQ = 1.8 V ± 0.1 V
Unit
Min
Nom
Max
OE to any Y/Y
ten
see Figure 12
8
ns
OE to any Y/Y
tdis
see Figure 12
8
ns
Cycle-to-Cycle Period Jitter
tjit(cc+)
see Figure 5
0
40
ps
tjit(cc–)
0
–40
ps
Static Phase Offset
t(
)
see Figure 6
–50
50
ps
Dynamic Phase Offset
t(
)dyn
see Figure 11
–50
50
ps
Output Clock Skew
tsk(o)
see Figure 10
40
ps
Period Jitter
tjit(per)
see Figure 8
–40
40
ps
Half -Period jitter
tjit(hper)
see Figure 9
–50
50
ps
Output Enable
slr(i)
see Figure 10
and Figure 12
0.5
V/ns
Input Clock Slew Rate, Measured Single Ended
1
2.5
4
Output Clock Slew Rate, Measured Single Ended
slr(o)
see Figure 10
and Figure 12
1.5
2.5
3
V/ns
Output Differential-Pair Cross Voltage
VOX
see Figure 3
(VDDQ/2) – 0.1
(VDDQ/2) + 0.1
V
SSC Modulation Frequency
30
33
kHz
SSC Clock Input Frequency Deviation
0
–0.5
PLL Loop Bandwidth (–3 dB from Unity Gain)
2
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC974FAR2 | 974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774FA | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774AE | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H73FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9893AE | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC970 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
| MPC972FA | 制造商:Freescale Semiconductor 功能描述: |
| MPC972H10 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC973 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。