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參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 395K |
| 代理商： | MPC96877VKR2 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC96877
Table 3. Absolute Maximum Ratings Over Free-Air Operating Range(1)
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Parameter
Value
Supply Voltage Range, VDDQ or AVDD
–0.5 V to 2.5 V
Input Voltage Range, VI(2), (3)
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5 V maximum.
–0.5 V to VDDQ + 0.5 V
Output Voltage Range, VO(1), (2)
–0.5 V to VDDQ + 0.5 V
Input Clamp Current, IIK (VI < 0 or VI > VDDQ)
±50 mA
Output Clamp Voltage, IOK (VO < 0 or VO > VDDQ)
±50 mA
Continuous Output Current, IO (VO = 0 to VDDQ)
±50 mA
Continuous Current through each VDDQ or GND
±100 mA
Storage Temperature Range, TSTG
–65
°C to 150°C
Table 4. Recommended Operating Conditions
Rating
Parameter
Affected Pins
Min
Nom
Max
Unit
Output Supply Voltage
VDDQ
1.7
1.8
1.9
V
Supply Voltage(1)
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and not timing parameters are guaranteed.
AVDD
VDDQ
Low-Level Input Voltage(2)
2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12 for definition. For CK and CK
the VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
VIL
OE, OS, CK, CK
0.35 x VDDQ
V
High-Level Input Voltage(2)
VIH
OE, OS, CK, CK
0.65 x VDDQ
High-Level Output Current
IOH
–9
mA
Low-Level Output Current
IOL
9
mA
Input Differential-Pair Cross Voltage
VIX
(VDDQ/2) –0.15
(VDDQ/2) +0.15
V
Input Voltage Level
VIN
–0.3
VDDQ +0.3
Input Differential-Pair Voltage(2)
(see Figure 9)
VID
DC
0.3
VDDQ +0.4
AC
0.6
VDDQ +0.4
Operating Free-Air Temperature
0
70
°C
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