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參數(shù)資料
| 型號： | MPC96877VKR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 395K |
| 代理商： | MPC96877VKR2 |
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MPC96877
Table 1. Pin Configuration
Pin
BGA
MLF
I/O
Function
AGND
G1
7
Analog ground
AVDD
H1
8
Analog power
CK
E1
4
Input
Clock input with a (10k to 100k) pulldown resistor
CK
E6
5
Input
Complimentary clock input with a (10k to 100k) pulldown resistor
FBIN
F6
27
Input
Feedback clock input
FBIN
26
Input
Complimentary Feedback clock input
FBOUT
H6
24
Output
Feedback clock output
FBOUT
G6
25
Output
Complimentary feeback clock output
OE
F5
22
Input
Output Enable (asynchronous)
OS
D5
21
Input
Output Select (tied to GND or VDD)
GND
B2, B3, B4, B5,
C2,C5,H2,H5,
J2, J3, J4, J5
10
Ground
VDDQ
D2, D3, D4, E2, E5,
F2, G2, G3, G4, G5
1, 6, 9, 15, 20, 23,
28, 31, 36
Logic and output power
Y[0:9]
A2, A1, D1, J1, K3,
A5, A6, D6, J6, K4
38, 39, 3, 11, 14,
34, 33, 29,19, 16
Output
Clock outputs
Y[0:9]
A3, B1, C1, K1, K2,
A4, B6, C6, K6, K5
37, 40, 2, 12, 13,
35, 32, 30, 18, 17
Output
Complimentary clock outputs
Table 2. Function Table
Inputs
Outputs
PLL
AVDD
OE
OS
CK
Y
FBOUT
GND
H
X
L
H
L
H
L
H
Bypassed / OFF
GND
H
X
H
L
H
L
H
L
Bypassed / OFF
GND
LHLH
LZ
L
H
Bypassed / OFF
GND
L
H
L
LZ(1)
Y7 Active
LZ(1)
Y7 Active
H
L
Bypassed / OFF
1.8 V Nominal
L
H
L
H
LZ(1)
LH
ON
1.8 V Nominal
L
H
L
LZ(1)
Y7 Active
LZ(1)
Y7 Active
HL
ON
1.8 V Nominal
H
X
L
H
L
H
L
H
ON
1.8 V Nominal
H
X
H
L
H
L
H
L
ON
1.8 V Nominal
X
L
LZ(1)
OFF
X
H
RESERVED
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