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參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 395K |
| 代理商： | MPC96877VKR2 |
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Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC96877
1. Total IDD = IDDQ + IADD = FCK* CPD * VDDQ, solving for CPD = (IDDQ + IADD)/(FCK * VDDQ) where FCK is the input Frequency, VDDQ is the
power supply and CPD is the Power Dissipation Capacitance.
Table 5. Electrical Characteristics Over Recommended Free-Air Operating Temperature Range
Description
Parameter
Affected Pins
Test Conditions
AVDD, VDDQ
Min
Max
Unit
All Inputs
VIK
II = –18 mA
1.7 V
–1.2
V
High Output Voltage
VOH
IOH = –100 A
1.7 to 1.9 V
VDDQ –0.2
V
IOH = –9 mA
1.7 V
1.1
Low Output Voltage
VOL
IOL = 100 A
1.7 to 1.9 V
0.1
V
IOL = 9 mA
1.7 V
0.6
Output Disable Current
IODL
OE = L, VODL = 100 mV
1.7 V
100
A
Output Differential Voltage
VOD
1.7 V
0.5
V
Input Leakage Current
II
CK, CK
VI = VDDQ or GND
1.9 V
± 250
A
OE, OS, FBIN, FBIN
VI = VDDQ or GND
1.9 V
± 10
Static Supply Current IDDQ + IADD
IDDLD
CK and CK = L
1.9 V
500
A
Dynamic Supply Current
IDDQ + IADD, see Note 1 for CPD
Calculation
IDD
CK and CK = 270 MHz all
outputs open
1.9 V
200
mA
Table 6. Timing Requirements Over Recommended Free-Air Operating Temperature Range
Timing Requirements
AVDD, VDDQ = 1.8 V ± 0.1 V
Unit
Min
Max
Operating Clock Frequency(1), (2)
1. The PLL must be able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing
parameters. (Used for low speed system debug.)
100
450
MHz
Application Clock Frequency(1), (3)
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
160
350
MHz
Input Clock Duty Cycle
40
60
%
Stabilization Time(4)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after
power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its
feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active
operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
15
s
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