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參數(shù)資料
| 型號： | MPC9658FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 9/9頁 |
| 文件大小： | 144K |
| 代理商： | MPC9658FA |
5
MPC9658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
526
Figure 10. Output–to–output Skew tSK(O)
Figure 11. Propagation delay (t(PD), static phase
offset) test reference
Figure 12. Output Duty Cycle (DC)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCCB2
GND
VCC
VCCB2
GND
tSK(O)
VCC
VCCB2
GND
tP
T0
DC = tP/T0 x 100%
VCMR =
VCC-1.3V
VCC
VCCB2
GND
t(PD)
PCLK
FB_IN
TJIT() = |T0-T1mean|
PCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 13. I/O Jitter
PCLK
VPP = 0.8V
Figure 14. Cycle–to–cycle Jitter
Figure 15. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN-TN+1|
TN+1
TJIT(PER) = |TN-1/f0|
T0
tF
tR
VCC=3.3V
2.4
0.55
Figure 16. Output Transition Time Test Reference
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