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參數(shù)資料
| 型號： | MPC9658FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9658FA |
5
MPC9658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
520
Table 1. PIN CONFIGURATION
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
VCO_SEL
Input
LVCMOS
Operating frequency range select
BYPASS
Input
LVCMOS
PLL and output divider bypass select
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0-9
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. FUNCTION TABLE
Control
Default
0
1
PLL_EN
1
Test mode with PLL bypassed. The reference clock
(PCLK) is substituted for the internal VCO output.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the VCO outputa
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the output dividers.
VCO_SEL
1
VCO
÷ 1 (High frequency range). fREF = fQ0-9 = 2 fVCO
VCO
÷ 2 (Low frequency range). fREF = fQ0-9 = 4
fVCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset the PLL feedback loop is
open. The VCO is tied to its lowest frequency. The
length of the reset pulse should be greater than one
reference clock cycle (PCLK).
a. PLL operation requires BYPASS=1 and PLL_EN=1.
Table 3. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
VOUT
DC Output Voltage
-0.3
VCC+0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage Temperature
-65
125
°C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
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