- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26839 > MPC9658FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MPC9658FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9658FA |
5
MPC9658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
524
Using the MPC9658 in zero–delay applications
Nested clock trees are typical applications for the
MPC9658. Designs using the MPC9658 as LVCMOS PLL fan-
out buffer with zero insertion delay will show significantly lower
clock skew than clock distributions developed from CMOS fan-
out buffers. The external feedback option of the MPC9658
clock driver allows for its use as a zero delay buffer. The PLL
aligns the feedback clock output edge with the clock input ref-
erence edge resulting a near zero delay through the device
(the propagation delay through the device is virtually elimi-
nated). The maximum insertion delay of the device in zero-
delay applications is measured between the reference clock
input and any output. This effective delay consists of the static
phase offset, I/O jitter (phase or long-term jitter), feedback path
delay and the output-to-output skew error relative to the feed-
back output.
Calculation of part-to-part skew
The MPC9658 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9658 are connected together, the maximum overall timing
uncertainty from the common PCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 4. MPC9658 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
PCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8. Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
± 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -214 ps to
224 ps relative to PCLK (fREF = 100 MHz, FB=÷4, tjit()=8 ps
RMS at fVCO = 400 MHz):
tSK(PP) =
[–70ps...80ps] + [–120ps...120ps] +
[(8ps
@ –3)...(8ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–214ps...224ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, figure 5
can be used for a more precise timing performance analysis.
Figure 5. Max. I/O Jitter versus frequency
VCO frequency [MHz]
200
250
300
350
400
450
500
20
15
10
5
0
FB=÷2
FB=÷4
I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
tjit(
)[ps]
RMS
Driving Transmission Lines
The MPC9658 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series termi-
nated or parallel terminated transmission lines can be used.
The parallel technique terminates the signal at the end of the
line with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9658 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can
drive multiple series terminated lines. Figure 6 “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC96877VKR2 | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| MPC974FAR2 | 974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774FA | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774AE | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H73FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9658FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9658FAR2 - Tape and Reel |
| MPC96877VK | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC96877VKR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC970 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。