- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄26839 > MPC9658FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC9658FA |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9658FA |
5
MPC9658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
523
APPLICATIONS INFORMATION
Programming the MPC9658
The MPC9658 supports output clock frequencies from 50 to
250 MHz. Two different feedback divider configurations can be
used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz
for stable and optimal operation. Two operating frequency
ranges are supported: 50 to 125 MHz and 100 to 250 MHz.
Table 7 illustrates the configurations supported by the
MPC9658. PLL zero-delay is supported if BYPASS=1,
PLL_EN=1 and the input frequency is within the specified PLL
reference frequency range.
Table 7. MPC9658 Configurations (QFB connected to FB_IN)
BYPAS
PLL_EN
VCO_SE
Operation
Frequency
S
_
L
p
Ratio
Output range (fQ0-9)
VCO
0
X
Test mode: PLL and divider bypass
fQ0-9 = fREF
0-250 MHz
n/a
1
0
Test mode: PLL bypass
fQ0-9 = fREF ÷ 2
0-125 MHz
n/a
1
0
1
Test mode: PLL bypass
fQ0-9 = fREF ÷ 4
0-62.5 MHz
n/a
1
0
PLL mode (high frequency range)
fQ0-9 = fREF
100 to 250 MHz
fVCO = fREF 2
1
PLL mode (low frequency range)
fQ0-9 = fREF
50 to 125 MHz
fVCO = fREF 4
Power Supply Filtering
The MPC9658 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9658 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCCA_PLL) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCC_PLL pin for the MPC9658. Figure 3
illustrates a typical power supply filter scheme. The MPC9658
frequency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming
that a minimum of 2.835V must be maintained on the VCC_PLL
pin.
Figure 3. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC9658
10 nF
RF = 5-15
CF
33...100 nF
RF
VCC
CF = 22 F
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3 “VCC_PLL Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9658 has several de-
sign features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
quate to eliminate power supply noise related problems in
most designs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC96877VKR2 | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| MPC974FAR2 | 974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774FA | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9774AE | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H73FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9658FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9658FAR2 - Tape and Reel |
| MPC96877VK | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC96877VKR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC970 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。