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參數(shù)資料
| 型號： | MPC9352FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 188K |
| 代理商： | MPC9352FAR2 |
MPC9352
TIMING SOLUTIONS
11
MOTOROLA
Table 11: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (
± 3s) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -445 ps to 395 ps relative to CCLK:
tSK(PP) =
[–200ps...150ps] + [–200ps...200ps] +
[(15ps
@ –3)...(15ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–445ps...395ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter,
Figure 9. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
Figure 9. Max. I/O Jitter versus frequency
Driving Transmission Lines
The MPC9352 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9352 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 10. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9352 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 10. Single versus Dual Transmission Lines
14
IN
MPC9352
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9352
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots in Figure 11. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC9352 output buffer is more
than sufficient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9352. The output waveform in Figure 11. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
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