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參數(shù)資料
| 型號： | MPC9352FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 188K |
| 代理商： | MPC9352FAR2 |
MPC9352
MOTOROLA
TIMING SOLUTIONS
10
Power Supply Filtering
The MPC9352 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCCA (PLL) power supply impacts the device
characteristics, for instance I/O jitter. The MPC9352 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCCA) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC9352. Figure 7. illustrates a typical power
supply filter scheme. The MPC9352 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the
VCCA pin. The resistor RF shown in Figure 7. “VCCA Power
Supply Filter” should have a resistance of 5–15
W (VCC=3.3V)
or 9-10
W (VCC=2.5V) to meet the voltage drop criteria.
Figure 7. VCCA Power Supply Filter
VCCA
VCC
MPC9352
10 nF
RF = 5-15 for VCC = 3.3V
RF = 9-10 for VCC = 2.5V
CF
33...100 nF
RF
VCC
CF = 22 F for VCC = 3.3V
CF = 22 F for VCC = 2.5V
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “VCCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9352 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9352 in zero–delay applications
Nested clock trees are typical applications for the
MPC9352. Designs using the MPC9352 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9352 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a
÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC9352 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9352 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 8. MPC9352 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
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