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參數(shù)資料
| 型號： | MPC9351FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 356K |
| 代理商： | MPC9351FAR2 |
MPC9351
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
113
Calculation of part-to-part skew
The MPC9351 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9351 are connected together, the maxi-
mum overall timing uncertainty from the common TCLK input
to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 3. MPC9351 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
± 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -251 ps to
351 ps relative to TCLK (VCC=3.3V and fVCO = 400 MHz):
tSK(PP) =
[–50ps...150ps] + [–150ps...150ps] +
[(17ps
@ –3)...(17ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–251ps...351ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number shown
in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O
jitter is frequency dependant with a maximum at the lowest
VCO frequency (200 MHz for the MPC9351). Applications us-
ing a higher VCO frequency exhibit less I/O jitter than the AC
characteristic limit. The I/O jitter characteristics in Figure 4 and
Figure 5 can be used to derive a smaller I/O jitter number at the
specific VCO frequency, resulting in tighter timing limits in
zero-delay mode and for part-to-part skew tSK(PP).
Figure 4. Max. I/O Jitter (RMS) versus frequency for
VCC=2.5V
Figure 5. Max. I/O Jitter (RMS) versus frequency for
VCC=3.3V
Power Supply Filtering
The MPC9351 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the VCCA
(PLL) power supply impacts the device characteristics, for
instance I/O jitter. The MPC9351 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCCA) of the device.The purpose of this design technique
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a digi-
tal system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCCA pin for the MPC9351. Figure 6 illus-
trates a typical power supply filter scheme. The MPC9351 fre-
quency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the VCCA
pin) is typically 3 mA (5 mA maximum), assuming that a mini-
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相關(guān)代理商/技術(shù)參數(shù) |
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| MPC9352 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
| MPC9352AC | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9352FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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