參數(shù)資料
型號： MPC9351FAR2
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, PLASTIC, LQFP-32
文件頁數(shù)： 2/10頁
文件大?。?/td> 356K
代理商： MPC9351FAR2
MPC9351
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
116
Figure 12. Propagation delay (tPD, static phase
offset) test reference
Figure 13. Propagation delay (tPD) test reference
Figure 14. Output Duty Cycle (DC)
Figure 15. Output–to–output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCCB2
GND
VCC
VCCB2
GND
tSK(O)
VCC
VCCB2
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCCB2
GND
VCC
VCCB2
GND
t()
TCLK
Ext_FB
VCC
VCCB2
GND
t()
PCLK
Ext_FB
PCLK
VCMR
Figure 16. Cycle–to–cycle Jitter
Figure 17. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN-TN+1|
TN+1
TJIT(P) = |TN-1/f0|
T0
tF
tR
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
Figure 18. I/O Jitter
Figure 19. Transition Time Test Reference
TJIT() = |T0-T1mean|
TCLK
Ext_FB
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
(PCLK)
2
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
MPC9352AC 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9352ACR2 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93H51FA PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93H51FAR2 PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93R52ACR2 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9352 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
MPC9352AC 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9352ACR2 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9352FA 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9352FAR2 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*