參數(shù)資料
型號: MPC9351FAR2
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, PLASTIC, LQFP-32
文件頁數(shù): 6/10頁
文件大?。?/td> 356K
代理商: MPC9351FAR2
MPC9351
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
111
DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Sym-
bol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
250
mV
LVPECL
VCMRa
Common Mode Range
PCLK, PCLK
1.0
VCC-0.6
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH=-15 mAb
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 - 20
W
IIN
Input Leakage Current
±200
A
VIN = VCC or GND
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
10
pF
Per Output
ICCA
Maximum PLL Supply Current
3.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. The MPC9351 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
100
50
25
200
100
50
MHz
fVCO
VCO Frequency
200
400
MHz
fMAX
Maximum Output Frequency
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
200
100
50
MHz
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMRb
Common Mode Range
PCLK, PCLK
1.2
VCC-0.6
V
LVPECL
tr, tf
TCLK Input Rise/Fall Time
1.0
ns
0.7 to 1.7V
t()
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
–100
0
+100
+300
ps
PLL locked
tsk(o)
Output-to-Output Skew
150
ps
DC
Output Duty Cycle
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
45
47.5
48.75
50
55
52.5
51.75
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8V
tPLZ, HZ
Output Disable Time
12
ns
tPZL, ZH
Output Enable Time
12
ns
BW
PLL closed loop bandwidth
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
4.0 – 15.0
2.0 – 7.0
0.7 – 2.0
MHz
–3dB point of
PLL transfer
characteristic
tJIT(CC)
Cycle-to-cycle jitter
÷ 4 feedback
Single Output Frequency Configuration
10
22
ps
RMS value
tJIT(PER)
Period Jitter
÷ 4 feedback
Single Output Frequency Configuration
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
6.0 – 25
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
a. AC characteristics apply for parallel output termination of 50
to VTT
b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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