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| 型號(hào)： | MPC9351FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 356K |
| 代理商： | MPC9351FAR2 |
MPC9351
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
112
APPLICATIONS INFORMATION
Programming the MPC9351
The MPC9351 clock driver outputs can be configured into
several divider modes, in addition the external feedback of the
device allows for flexibility in establishing various input to out-
put frequency relationships. The output divider of the four out-
put groups allows the user to configure the outputs into 1:1,
2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers
ensure that the output duty cycle is always 50%. “Output Fre-
quency Relationship for an Example Configuration” illustrates
the various output configurations, the table describes the out-
puts using the input clock frequency CLK as a reference.
The output division settings establish the output relation-
ship, in addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback fre-
quency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while the
VCO frequency range is specified from 200 MHz to 400 MHz
and should not be exceeded for stable operation.
Output Frequency Relationshipa for an Example Configuration
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC
QD
0
2 * CLK
CLK
0
1
2 * CLK
CLK
÷ 2
0
1
0
4 * CLK
2 * CLK
CLK
2* CLK
0
1
4 * CLK
2 * CLK
CLK
0
1
0
2 * CLK
CLK
÷ 2
CLK
0
1
0
1
2 * CLK
CLK
÷ 2
CLK
÷ 2
0
1
0
4 * CLK
CLK
2 * CLK
0
1
4 * CLK
CLK
1
0
CLK
1
0
1
CLK
÷ 2
1
0
1
0
2 * CLK
CLK
2 * CLK
1
0
1
2 * CLK
CLK
1
0
CLK
÷ 2
CLK
1
0
1
CLK
÷ 2
CLK
÷ 2
1
0
2 * CLK
CLK
2 * CLK
1
2 * CLK
CLK
a. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
available by the connection of QA to the feedback input (EXT_FB).
Using the MPC9351 in zero–delay applications
Nested clock trees are typical applications for the
MPC9351. For these applications the MPC9351 offers a differ-
ential LVPECL clock input pair as a PLL reference. This allows
for the use of differential LVPECL primary clock distribution
devices such as the Motorola MC100EP111 or MC10EP222,
taking advantage of its superior low-skew performance. Clock
trees using LVPECL for clock distribution and the MPC9351 as
LVCMOS PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions devel-
oped from CMOS fanout buffers.
The external feedback option of the MPC9351 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the MPC9351
in zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset (SPO or t()), I/O jitter (tJIT(), phase or
long-term jitter), feedback path delay and the output-to-output
skew (tSK(O) relative to the feedback output.
MPC9351 zero–delay configuration (feedback of QD4)
MPC9351
TCLK
QA
fref = 100 MHz
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
2 x 100 MHz
4 x 100 MHz
100 MHz (Feedback)
1
0
2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9352 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
| MPC9352AC | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9352FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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