參數(shù)資料
型號(hào)： MPC9331FA
廠商： MOTOROLA INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 8/10頁(yè)
文件大?。?/td> 149K
代理商： MPC9331FA
MPC9331
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
94
Table 9. MPC9331 Example Configurations (External Feedback and PWR_DN = 0)
PLL
Feedback
frefa [MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
100 - 240
0
fref
(100-240 MHz)
fref
(100-240 MHz)
fref
÷ 2 (50-120 MHz)
VCO
÷ 2b
0
1
fref
(100-240 MHz)
fref
(100-240 MHz)
fref
÷ 3 (33.3-80 MHz)
VCO
÷ 2b
0
1
0
fref
(100-240 MHz)
fref
÷ 2 (50-120 MHz)
fref
÷ 2 (50-120 MHz)
0
1
fref
(100-240 MHz)
fref
÷ 2 (50-120 MHz)
fref
÷ 3 (33.3-80 MHz)
50 - 120
1
0
fref
(50-120 MHz)
fref
2 (100-240 MHz)
fref
(50-120 MHz)
VCO
÷ 4c
1
0
1
fref
(50-120 MHz)
fref
2 (100-240 MHz)
fref
2÷3 (33.3-80 MHz)
VCO
÷ 4c
1
0
fref
(50-120 MHz)
fref
(100-240 MHz)
fref
(50-120 MHz)
1
fref
(50-120 MHz)
fref
(100-240 MHz)
fref
2 ÷ 3 (33.3-80 MHz)
33.3-80
0
1
fref
3 (100-240 MHz)
fref
3 (100-240 MHz)
fref
(33.3-80 MHz)
VCO
÷ 6d
0
1
fref
3 (100-240 MHz)
fref
3 ÷ 2 (50-120 MHz) fref
(33.3-80 MHz)
VCO
÷ 6d
1
0
1
fref
3 ÷ 2 (50-120 MHz) fref 3 (100-240 MHz)
fref
(33.3-80 MHz)
1
fref
3 ÷ 2 (50-120 MHz) fref 3 ÷ 2 (50-120 MHz) fref
(33.3-80 MHz)
a. fref is the input clock reference frequency (CCLK or PCLK)
b. QAx connected to FB_IN and FSELA = 0, PWR_DN = 0
c. QAx connected to FB_IN and FSELA = 1, PWR_DN = 0
d. QCx connected to FB_IN and FSELC = 1, PWR_DN = 0
Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1)
PLL
Feedback
frefa [MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
25.0 - 60.0
1
0
fref
(25-60 MHz)
fref
2 (50-120 MHz)
fref
(2.25-60 MHz)
VCO
÷ 8b
1
0
1
fref
(25-60 MHz)
fref
2 (50-120 MHz)
fref
2÷3 (16.6-40 MHz)
VCO
÷ 8b
1
0
fref
(25-60 MHz)
fref
(25-60 MHz)
fref
(25-60 MHz)
1
fref
(25-60 MHz)
fref
(25-60 MHz)
fref
2÷3 (16.6-40 MHz)
16.67 - 40
0
1
fref
3 (50-120 MHz)
fref
3 (50-120 MHz)
fref
(16.67-40 MHz)
VCO
÷ 12c
0
1
fref
3 (50-120 MHz)
fref
3 ÷ 2 (25-60
MHz)
fref
(16.67-40 MHz)
1
0
1
fref
3 ÷ 2 (25-60
MHz)
fref
3 (50-120 MHz)
fref
(16.67-40 MHz)
1
fref
3 ÷ 2 (25-60
MHz)
fref
3 ÷ 2 (25-60
MHz)
fref
(16.67-40 MHz)
a. fref is the input clock reference frequency (CCLK or PCLK)
b. QAx connected to FB_IN and FSELA = 1, PWR_DN = 1
c. QCx connected to FB_IN and FSELC = 1, PWR_DN = 1
2
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參數(shù)描述
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MPC9350 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER
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MPC9350ACR2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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