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參數(shù)資料
| 型號： | MPC9331FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 149K |
| 代理商： | MPC9331FA |
MPC9331
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
93
APPLICATIONS INFORMATION
Output power down (PWR_DN) timing diagram
VCO÷2
VCO÷4
QAx (÷2)
QBx (÷4)
QBCx (÷6)
PWR_DWN
Output clock stop (CLK_STOP) timing diagram
QAx (÷2)
QBx (÷4)
QCx (÷6)
CLK_STOP0
CLK_STOP1
QAx (÷2)
QBx (÷4)
QCx (÷6)
Programming the MPC9331
The MPC9331 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider con-
figurations can be used to achieve the desired input to output
frequency relationship. The feedback frequency and divider
should be used to situate the VCO in the frequency lock range
between 200 and 480 MHz for stable and optimal operation.
The FSELA, FSELB, FSELC and PWR_DN pins select the de-
sired output clock frequencies. Possible frequency ratios of the
reference clock input to the outputs are 4:1, 3:1, 2:1, 1:1, 1:2,
2:3 and 3:2. Table 8 illustrates the various output configura-
tions and frequency ratios supported by the MPC9331. See
also Table 8 and 9 for further reference.
Table 8. MPC9331 Example Configurations (Internal Feedback and FB_SEL = 0)
frefa [MHz]
PWR_DN
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
fref
4 (100-240 MHz)
fref
4 (100-240 MHz)
fref
2 (50-120 MHz)
0
1
fref
4 (100-240 MHz)
fref
4 (100-240 MHz)
fref
4÷3(33.3-80 MHz)
0
1
0
fref
4 (100-240 MHz)
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
0
1
fref
4 (100-240 MHz)
fref
2 (50-120 MHz)
fref
4÷3(33.3-80 MHz)
0
1
0
fref
2 (50-120 MHz)
fref
4 (100-240 MHz)
fref
2 (50-120 MHz)
0
1
0
1
fref
2 (50-120 MHz)
fref
4 (100-240 MHz)
fref
4÷3(33.3-80 MHz)
0
1
0
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
25.0 - 60.0
0
1
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
fref
4÷3(33.3-80 MHz)
25.0 60.0
1
0
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
fref
(25.0-60 MHz)
1
0
1
fref
2 (50-120 MHz)
fref
2 (50-120 MHz)
fref
2÷3 (16.67-40 MHz)
1
0
1
0
fref
2 (50-120 MHz)
fref
(25.0-60 MHz)
fref
(25.0-60 MHz)
1
0
1
fref
2 (50-120 MHz)
fref
(25.0-60 MHz)
fref
2÷3(16.67-40 MHz)
1
0
fref
(25.0-60 MHz)
fref
2 (50-120 MHz)
fref
(25.0-60 MHz)
1
0
1
fref
(25.0-60 MHz)
fref
2 (50-120 MHz)
fref
2÷3(16.67-40 MHz)
1
0
fref
(25.0-60 MHz)
fref
(25.0-60 MHz)
fref
(25.0-60 MHz)
1
fref
(25.0-60 MHz)
fref
(25.0-60 MHz)
fref
2÷3(16.67-40 MHz)
a. fref is the input clock reference frequency (CCLK or PCLK)
2
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