- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26838 > MPC9331FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MPC9331FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 149K |
| 代理商： | MPC9331FA |
MPC9331
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
92
Table 7. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input reference frequency
÷2 feedback
PLL mode, external feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
PLL mode, internal feedback
(
÷8 feedback)
Input reference frequency in PLL bypass modeb
100.0
50.0
33.3
25.0
16.67
25.0
240.0
120.0
80.0
60.0
40.0
60.0
240
MHz
PLL locked
fVCO
VCO lock frequency rangec
200
480
MHz
fMAX
Output Frequency
÷2 output
÷4 output
÷6 output
÷8 output
÷12 output
100.0
50.0
33.3
25.0
16.67
240.0
120.0
80.0
60.0
40.0
MHz
PLL locked
VPP
Peak-to-peak input voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMRd
Common Mode Range
PCLK, PCLK
1.2
VCC - 0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Widthe
2.0
ns
tR, tF
CCLK Input Rise/Fall Timef
1.0
ns
0.8 to 2.0V
t()
Propagation Delay
CCLK to FB_INg
(static phase offset)
PCLK to FB_INg
CCLK or PCLK to FB_INh
–250
–180
–3.0
–130
–30
–50
+120
+3.0
ps
°
FB_SEL = 1
and PLL locked
tsk(O)
Output-to-output Skew
150
ps
DC
Output duty cyclei
(T
B2)–500
T
B2
(T
B2)+500
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
8.0
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitterj
200
ps
tJIT(PER)
Period Jitterj
125
ps
tJIT()
I/O Phase Jitter
RMS (1
σ)
25
ps
BW
PLL closed loop bandwidthk
÷ 4 feedback
PLL mode, external feedback
÷ 6 feedback
÷ 8 feedback
÷12 feedback
2.0–8.0
1.2–4.0
1.0–3.0
0.7–2.0
MHz
tLOCK
Maximum PLL Lock Time
10
ms
NOTES:
a
AC characteristics apply for parallel output termination of 50
to VTT.
b
In bypass mode, the MPC9331 divides the input reference clock.
c
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
dVCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
e
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
f
The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only
be guaranteed if tR, tF are within the specified range.
g
Data valid for fREF=50 MHz and a PLL feedback of ÷8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1).
h
Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [°] ÷ (fREF 360°).
i
Output duty cycle is DC = (0.5
± 500 ps fOUT) 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%).
j
All outputs in
÷4 divider configuration.
k
-3 dB point of PLL transfer characteristics.
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9331FAR2 | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9351FAR2 | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9352AC | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9352ACR2 | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93H51FA | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9331FAR2 | 功能描述:IC CLOCK GEN 1:6 PLL LV 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC9350 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350AC | 功能描述:時鐘驅(qū)動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。