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參數(shù)資料
| 型號(hào)： | MPC9331FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 149K |
| 代理商： | MPC9331FA |
MPC9331
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
90
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
PCLK, PCLK
Input
LVPECL
Differential PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
FB_SEL
Input
LVCMOS
Feedback select
REF_SEL
Input
LVCMOS
Reference clock select
PWR_DN
Input
LVCMOS
Output frequency and power down select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
CLK_STOP0-1
Input
LVCMOS
Clock output enable/disable
OE/MR
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0-1, QB0-1, QC0-1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to
use external RC filter for the analog power supply pin VCC_PLL. Please
see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
PCLK is the PLL reference clock
CCLK is the PLL reference clock
FB_SEL
1
Internal PLL feedback of 8. fVCO = 8 * fref
External feedback. Zero-delay operation enabled for
CCLK or PCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9331 is
fully static and no minimum frequency limit applies. All
PLL related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
PWR_DN
1
VCO
÷ 1 (High output frequency range)
VCO
÷ 2 (Low output frequency range)
FSELA
0
Output divider
÷ 2
Output divider
÷ 4
FSELB
0
Output divider
÷ 2
Output divider
÷ 4
FSELC
0
Output divider
÷ 4
Output divider
÷ 6
OE/MR
1
Outputs disabled (high-impedance state) and reset of
the device. During reset in external feedback
configuration, the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The MPC9331
requires reset after any loss of PLL lock. Loss of PLL
lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be
greater than one reference clock cycle (CCLK or
PCLK). Reset does not affect PLL lock in internal
feedback configuration.
Outputs enabled (active)
CLK_STOP[0:1]
11
See Table 3
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Tables 8 – 10 for supported frequency ranges and output to input frequency ratios.
2
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| MPC9350 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350AC | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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