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參數(shù)資料
| 型號(hào)： | MPC9315FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 401K |
| 代理商： | MPC9315FA |
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Advanced Clock Drivers Devices
12
Freescale Semiconductor
MPC9315
Figure 15. Propagation delay (t(), SPO) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 17. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
CC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CLK0, 1
FB0, 1
VCC ÷ 2
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Period Jitter
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TN
TN+1
TJIT(PER) = |TN–1/f0|
T0
tF
tR
VCC=3.3 V
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
Figure 20. I/O Jitter
Figure 21. Output Transition Time Test Reference
TJIT() = |T0–T1mean|
TCLK0, 1
FB0, 1
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
TJIT(CC) = |TN–TN+1|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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| MPC9330 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| MPC9330AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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