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參數(shù)資料
| 型號： | MPC9315FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 401K |
| 代理商： | MPC9315FA |
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC9315
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = -40° to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
÷2 feedback
÷4 feedback
PLL bypass mode
37.50
18.75
0
80
40
TBD
MHz
PLL locked
VCCA = GND
fVCO
VCO Lock Range
75(2)
2.
÷1 feedback is responsible for VCC = 2.5 V operation. Please see application section for I/O jitter versus VCO frequency characteristics.
160(2)
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
÷4 output
75
37.50
18.75
160
80
40
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CLK0, CLK1 Input Rise/Fall Time
1.0
ns
0.7 to 1.7 V
t()
Propagation Delay
CLK0 or CLK1 to FB
(Static Phase Offset)
-150
+150
ps
PLL locked
tSK()
Output-to-Output Skew
Within one bank
Any output
80
120
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
12
ns
tPZL, LZ
Output Enable Time
12
ns
BW
PLL closed loop bandwidth
÷2 feedback
÷4 feedback
1.0 - 10
0.4 - 3.0
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
(1
σ)
10
22
ps
RMS value
tJIT(PER) Period Jitter
(1
σ)
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
(1
σ)
10 - 25(3)
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
TBD
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
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|---|---|
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| MPC9330AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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