- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2099 > MPC9315AC (IDT, Integrated Device Technology Inc)IC PLL CLOCK GEN/DRIVER 32-LQFP PDF資料下載
參數(shù)資料
| 型號： | MPC9315AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:8 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9315 REVISION 5 JANUARY 24, 2013
10
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Power Supply Filtering
The MPC9315 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
VCCA (PLL) power supply impacts the device characteristics,
for instance I/O jitter. The MPC9315 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCCA) of the device. The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult
to minimize noise on the power supplies, a second level of
isolation may be required. The simple but effective form of
isolation is a power supply filter on the VCCA pin for the
MPC9315. Figure 10 illustrates a typical power supply filter
scheme. The MPC9315 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range. Therefore the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet, the ICCA current (the current
sourced through the VCCA pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 2.325 V (VCC =
3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin.
270
(VCC = 3.3 V) or 9-10 (VCC = 2.5 V) to meet the
voltage drop criteria.
Figure 10. VCCA Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 10, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9315 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise-related problems in most designs.
Driving Transmission Lines
The MPC9315 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9315 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines. Figure 11
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme, the fanout of the MPC9315 clock driver is
effectively doubled due to its capability to drive multiple lines.
Figure 11. Single versus Dual Transmission Lines
The waveform plots in Figure 11 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9315 output buffer
is more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9315. The output waveform
in Figure 12 shows a step in the waveform; this step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36
series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VCCA
VCC
MPC9315
RF = 270 for VCC = 3.3 V
CF
RF
VCC
CF = 1 F for VCC = 3.3 V
CF = 22 F for VCC = 2.5 V
RF = 9–10 for VCC = 2.5 V
10 nF
33...100 nF
14
IN
MPC9315
Output
Buffer
RS = 36
ZO = 50
14
IN
MPC9315
Output
Buffer
RS = 36
ZO = 50
RS = 36
ZO = 50
OutA
OutB0
OutB1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9350AC | IC PLL CLOCK DRIVER LV 32-LQFP |
| MPC941AE | IC CLOCK BUFFER MUX 1:27 48-LQFP |
| MPC9443FAR2 | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| MPC9446FAR2 | IC CLK BUFF DVDR MUX 2:10 32LQFP |
| MPC9447ACR2 | IC CLOCK BUFFER MUX 2:9 32-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9315ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。