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參數(shù)資料
| 型號： | MPC9315AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 標準包裝： | 250 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:8 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9315 REVISION 5 JANUARY 24, 2013
9
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Using the MPC9315 in Zero-Delay Applications
The external feedback option of the MPC9315 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9315 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Calculation of Part-to-Part Skew
The MPC9315 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9315 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 7. MPC9315 max. Device-to-Device Skew
Due to the statistical nature of I/O jitter, an RMS value (1
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (
3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –300 ps to +300 ps relative to TCLK (VCC =3.3 V
and fVCO = 160 MHz):
tSK(PP) = [–150ps...150ps] + [–150ps...150ps] +
[(10ps @ –3)...(10ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [–300ps...300ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (10 ps
RMS). I/O jitter is frequency-dependant with a maximum at
the lowest VCO frequency (160 MHz for the MPC9315).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew tSK(PP).
Figure 8. Max. I/O Jitter (RMS) versus
Frequency for VCC = 2.5 V
Figure 9. Max. I/O Jitter (RMS) versus
Frequency for VCC = 3.3 V
Table 12. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
TCLKCOMMON
30
25
20
15
10
5
0
75
100
125
150
175
200
VCO frequency [MHz]
t JI
T()
[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
30
25
20
15
10
5
0
75
100
125
150
175
200
t JI
T(
)
[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
VCO frequency (MHz)
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