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參數(shù)資料
| 型號： | MPC9315AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:8 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9315 REVISION 5 JANUARY 24, 2013
7
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
APPLICATIONS INFORMATION
Programming the MPC9315
The PLL of the MPC9315 supports output clock
frequencies from 18.75 to 160 MHz. Different feedback and
output divider configurations can be used to achieve the
desired input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO in
the frequency range between 75 and 160 MHz for stable and
optimal operation. The FSELA, FSELB, FSELC pins select
the desired output clock frequencies. Possible frequency
ratios of the reference clock input to the outputs are 1:1, 1:2,
illustrate the various output configurations and frequency
ratios supported by the MPC9315. PSELA controls the output
phase of the QA0 and QA1 outputs, allowing the user to
generate inverted clock signals synchronous to non-inverted
clock signals. See also Example Configurations for the
MPC9315 for further reference.
Table 9. Output Frequency Relationship for QA0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
2
0
1
CLK
4
0
1
0
CLK
2
CLK
2
0
1
CLK
2
CLK
4
1
0
CLK
2 * CLK
CLK
1
0
1
CLK
2 * CLK
CLK
2
1
0
CLK
1
CLK
2
Table 10. Output Frequency Relationship for QB0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
2
0
1
CLK
4
0
1
0
2 * CLK
CLK
0
1
2 * CLK
CLK
2
1
0
CLK
2
CLK
2
1
0
1
CLK
2
CLK
4
1
0
CLK
1
CLK
2
Table 11. Output Frequency Relationship for QC0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
2 * CLK
CLK
0
1
4 * CLK
CLK
0
1
0
2 * CLK
CLK
0
1
4 * CLK
2 * CLK
CLK
1
0
CLK
2 * CLK
CLK
1
0
1
2 * CLK
4 * CLK
CLK
1
0
CLK
1
2 * CLK
CLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9315ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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