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參數(shù)資料
| 型號(hào)： | MPC8540PXAQFC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 97/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
92
Freescale Semiconductor
System Design Information
17.8 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE Std 1149.1 specification, but is provided on all processors that implement the Power Architecture.
The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.
Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the
common on-chip processor (COP) function.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 54 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 54, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 54 is common to
all known emulators.
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