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| 型號： | MPC8540PXALDB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 99/104頁 |
| 文件大?。?/td> | 2133K |
| 代理商： | MPC8540PXALDB |
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MPC8540 Integrated Processor Hardware Specifications, Rev. 3.1
94
Freescale Semiconductor
System Design Information
resistor of approximately 20 k
. This value should permit the 4.7-k resistor to pull the configuration pin to a valid
logic low level. The pull-up resistor is enabled only during HRESET (and for platform/system clocks after HRESET
deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing
functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all
configuration bits treated this way has been encoded such that a high voltage level puts the device into the default
state and external resistors are needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the
pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
17.7 Pull-Up Resistor Requirements
The MPC8540 requires high resistance pull-up resistors (10 k
is recommended) on open drain type pins including
EPIC interrupt pins. I2C open drain type pins should be pulled up with ~1 k
resistors.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in
Figure 54. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal
operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that could cause
this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong enough to restore
these signals to a logical 1 during reset.
Three test pins also require pull-up resistors (100
- 1 k). These pins are L1_TSTCLK, L2_TSTCLK, and
LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine
operation.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
17.8 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE
1149.1 specification, but is provided on all processors that implement the PowerPC architecture. The MPC8540
requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with
normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS
signals, generally systems will assert TRST during power-on reset. Because the JTAG interface is also used for
accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 54 allows the COP to independently assert HRESET or TRST, while ensuring that
the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied
to HRESET so that it is asserted when the system reset signal (HRESET) is asserted.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8540PXAQFB | 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540PXAQFC | 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VT533JB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VT667LB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VT667LC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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