參數(shù)資料
型號: MPC8540PXALDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 96/104頁
文件大?。?/td> 2133K
代理商: MPC8540PXALDB
MPC8540 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
91
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8540.
17.1 System Clocking
The MPC8540includes twoPLLs.
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency
ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as
2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio between
the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 and AVDD2,
respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived
directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide three
independent filter circuits as illustrated in Figure 52, one to each of the three AVDD pins. By providing independent
filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It
should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall,
1993), multiple small capacitors of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled
from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the
periphery of the 783 FC-PBGA footprint, without the inductance of vias.
Figure 52 shows the PLL power supply filter circuit.
Figure 52. PLL Power Supply Filter Circuit
17.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8540 can generate transient power
surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must
be prevented from reaching other components in the MPC8540 system, and the MPC8540 itself requires a clean,
tightly regulated source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the MPC8540. These decoupling capacitors
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
相關(guān)PDF資料
PDF描述
MPC8540PXAPDB 32-BIT, 833 MHz, MICROPROCESSOR, PBGA783
MPC8540VT667LB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
MPC8540CPX667LB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
MPC8540CVT667LC 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
MPC8540PX667JB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
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MPC8540VT667LC 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324