參數(shù)資料
型號: MPC8377EVRANGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 66/124頁
文件大?。?/td> 1462K
代理商: MPC8377EVRANGA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
46
Freescale Semiconductor
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
tSFSCLKL =20 ns:
tCLK_DELAY + 5 0 < 20 + tDATA_DELAY
tCLK_DELAY < 15 + tDATA_DELAY
11.2.1.3
Full-Speed Write Combined Formula
The following equation is the combined formula to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tIH tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY tISU tSFSKHOV
11.2.2
Full-Speed Input Path (Read)
Figure 28 provides the data and command input timing diagram.
Figure 28. Full Speed Input Path
11.2.2.1
Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK
tCLK_DELAY + tDATA_DELAY < tSFSCK tODLY tSFSIVKH tINT_CLK_DLY
11.2.2.2
Full-Speed Read Meeting Hold (Minimum Delay)
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH
tCLK_DELAY
Output from the
SD CLK at
the Card Pin
SD Card Pins
tSFSIVKH
tSFSIXKH
Driving
Edge
Sampling
Edge
tOH
tDATA_DELAY
tODLY
tSFSCK (Clock Cycle)
(MPC8377E Input Hold)
SD CLK at the
MPC8377E Pin
Input at the
MPC8377E Pins
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