參數(shù)資料
型號(hào)： MPC8377EVRANGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 33/124頁
文件大?。?/td> 1462K
代理商： MPC8377EVRANGA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
16
Freescale Semiconductor
DDR1 and DDR2 SDRAM
6
DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8377E. Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V2, 5
I/O termination voltage
VTT
MVREF –0.04
MVREF +0.04
V
Input high voltage
VIH
MVREF + 0.140
GVDD +0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.140
V
—
Output leakage current
IOZ
–40
40
μA4
Output high current (VOUT =1.40V)
IOH
–13.4
—
mA
—
Output low current (VOUT =0.3 V)
IOL
13.4
—
mA
—
Note:
1 GV
DD is expected to be within 50 mV of the DRAM GVDD at all times.
2 MV
REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3 V
TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4 Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
5 See AN3665, MPC837xE Design Checklist, for proper DDR termination.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
Note:
1 This parameter is sampled. GV
DD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
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