參數(shù)資料
型號： MPC8377EVRANGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 27/124頁
文件大?。?/td> 1462K
代理商： MPC8377EVRANGA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
122
Freescale Semiconductor
Document Revision History
27 Document Revision History
Table 86 provides a revision history for this hardware specification.
Revision
Date
Substantive Change(s)
2
10/2009
In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.
In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.
In Table 10, removed overbar from CFG_CLKIN_DIV.
In Table 16, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400
μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
Specifications,” corrected titles from “Transmitter” to “Receiver”.
to VDD pin.
In Table 73, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
In Table 78, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
In Table 79, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
In Section 20.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,
1
02/2009
In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
In Table 5, “MPC8377E Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667
MHz.
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,
MPC837xE Design Checklist.
In Table 20, updated tDDKHCX minimum value for 333 MHz to 2.40.
In Table 71, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 13.
In Table 73, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for
core_clk.
In Table 79, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
Updated part numbering information in AF column in Table 83, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
In Table 84, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
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