參數(shù)資料
型號(hào): MPC8349EZUAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 89/115頁
文件大?。?/td> 1228K
代理商: MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
75
Clocking
Table 50 provides the operating frequencies for the MPC8349E TBGA under recommended operating
conditions (see Table 60).
18.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 51 shows the multiplication factor
encodings for the system PLL.
Table 50. Operating Frequencies for TBGA
Characteristic 1
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the
resulting csb_clk, MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or
minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and
SCCR[USBMPHCM] must be programmed such that the maximum internal operating frequency of the
Security core and USB modules will not exceed their respective value listed in this table.
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (core_clk)
TBD–400
TBD–533
TBD–667
MHz
Coherent system bus frequency
(csb_clk)
100–266
100–300
(333 TBD)
100–333
MHz
DDR memory bus frequency
(MCK) 2
2
The DDR data rate is 2x the DDR memory bus frequency.
100–133
(166 TBD)
100–166.67
MHz
Local bus frequency
(LCLKn) 3
3
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which
is in turn 1x or 2x the ccb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
(166 TBD)
16.67–133
MHz
PCI input frequency (CLKIN or
PCI_CLK)
25–66
MHz
Security core maximum internal
operating frequency
133
166
MHz
USB_DR, USB_MPH maximum
internal operating frequency
133
(166 TBD)
166
MHz
Table 51. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
× 16
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111
× 7
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