參數(shù)資料
型號(hào): MPC8349EZUAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 28/115頁
文件大?。?/td> 1228K
代理商: MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
2
Freescale Semiconductor
Overview
1
Overview
This section provides a high-level overview of the MPC8349E features. Figure 1 shows the major
functional units within the MPC8349E.
Figure 1. MPC8349E Block Diagram
Major features of the MPC8349E are as follows:
Embedded PowerPC processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement the PowerPC
architecture
DDR SDRAM memory controller
— Programmable timing supporting DDR-1 SDRAM
— 32-or 64-bit data interface, up to 333 MHz data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
Coherent System Bus
PCI1
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
MII, GMII, TBI,
RTBI, RGMII
SPI
Serial
IRQs
SDRAM
DDR
ROM
10/100/1Gb
I2C
TSEC
I2C Interfaces
TSEC
DDR Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
DUART
e300 Core
DMA Controller
Serial Peripheral
Interface
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI2
0/32b PCI Controller
Security Engine
Arbiter Bus
Monitor
SEC
USB Hi-Speed
Host Device
General Purpose I/O
USB0
USB1
GPIO
SDRAM
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