參數(shù)資料
型號: MPC8349EZUAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 20/115頁
文件大?。?/td> 1228K
代理商: MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
12
Freescale Semiconductor
RESET Initialization
Table 7 provides the PLL and DLL lock times.
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the MPC8349E is in PCI agent
mode
4—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to
negation of HRESET
0—
ns
Time for the MPC8349Eto turn offPOR config signals
with respect to the assertion of HRESET
—4
ns
3
Time for the MPC8349E to turn onPOR config signals
with respect to the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8349E is In PCI
host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of
CFG_CLKIN_DIV. See the MPC8349E Integrated Host Processor Reference Manual Rev. 0 for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8349E is in PCI host
mode. See the MPC8349E Integrated Host Processor Reference Manual Rev. 0 for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 7. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
100
s
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).
A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 18, “Clocking,” for more information.
Table 6. RESET Initialization Timing Specifications (continued)
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