參數(shù)資料
型號(hào): MPC8313E-RDBB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 19/99頁(yè)
文件大?。?/td> 0K
描述: BOARD CPU 8313E VER 2.1
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8313E
所含物品:
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
26
Freescale Semiconductor
8.2.1.4
RMII Receive AC Timing Specifications
This table provides the RMII receive AC timing specifications.
This table provides the AC test load.
Figure 12. AC Test Load
This table shows the RMII receive AC timing diagram.
Figure 13. RMII Receive AC Timing Diagram
Table 29. RMII Receive AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
REF_CLK clock period
tRMX
—20—
ns
REF_CLK duty cycle
tRMXH/tRMX
35
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
ns
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
4.0
ns
REF_CLK clock fall time VIH(max) to VIL(min)
tRMXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock
reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect
to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
Output
Z0 = 50
NVDD/2
RL = 50
REF_CLK
RXD[1:0]
tRMRDXKH
tRMX
tRMXH
tRMXR
tRMXF
CRS_DV
RX_ER
tRMRDVKH
Valid Data
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