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參數(shù)資料
| 型號： | MPC8245LZU350X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 620K |
| 代理商： | MPC8245LZU350X |
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MPC8245 Integrated Processor Hardware Specications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2 Thermal Characteristics
Table 6 provides the package thermal characteristics for the MPC8245.
1.4.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC8245. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Table 7 and tested for conformance to the
AC specications for that frequency. The processor core frequency is determined by the bus
(PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0–4] signals. Parts are sold by
maximum processor core frequency; see Section 1.9, “Ordering Information”.
Table 7 provides the operating frequency information for the MPC8245.
Table 6. Package Thermal Characteristics
Characteristic
Symbols
Value
Units
Die Junction-to-Case Thermal Resistance
θJC
1.8
°C/W
Die Junction-to-Board Thermal Resistance
θJB
4.8
°C/W
Notes:
1
Refer to Section 1.7, “System Design Information,” for more details about thermal management
.
Table 7. Operating Frequency
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3V
Characteristic1
266 MHz
300 MHz
333 MHz
350 MHz
Units
Vdd/AVdd/AVdd2 = 1.8/2.0 ±
100 mV
Vdd/AVdd/AVdd2 = 2.0 ± 100 mV
Processor Frequency
(CPU)
100 - 266
100 - 300
100 -333
100 - 350
MHz
Processor VCO
Frequency (CPU)3
200 - 532
200 - 600
200 - 666
200 - 700
MHz
Memory Bus Frequency
33 - 133
33 -1002
33 - 133
33 - 1002
MHz
PCI Input Frequency
25 – 66
MHz
Notes:
1
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–4] settings must be chosen such that the
resulting peripheral logic/ memory bus frequency and CPU (core) frequencies do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–4] signal descrip-
tion in Section 1.6, “PLL Conguration,” for valid PLL_CFG[0–4] settings and PCI_SYNC_IN frequen-
cies.
2
There are no available PLL_CFG[0–4] settings which support 133 MHz memory interface operation at
300 MHz CPU and 350 MHz operation, since the multipliers do not allow a 300:133 and 350:133 ratio
relation. However, running these parts are slower speeds may produce ratios that will run above 100
MHz. Please see Table 17 for the PLL settings.
3
of various PLL congurations.
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