參數(shù)資料
型號： MPC8245LZU350X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù)： 40/60頁
文件大?。?/td> 620K
代理商： MPC8245LZU350X
MPC8245 Integrated Processor Hardware Specications
45
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
1.7.8 MPC8245 Compatibility with MPC8240
The MPC8245 AC timing specications are backwards compatible with those of the MPC8240, except for
the requiremnts of item 11 of Table 9. Timing adjustments are needed as specied for Tos
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM Flow-Through memory interface.
The nominal core Vdd power supply changes from 2.5 V on the MPC8240 to 2.0 V on the MPC8245. (See
Table 2 for details)
The MPC8245 PLL_CFG[0–4] setting 0x02 (0b00010) has a different “PCI to Mem” and “Mem to CPU”
multiplier ratio than the same setting on the MPC8240 and thus is not backwards compatible. See Table 17
for details.
The MPC8245 PLL_CFG[0–4] settings 0x08 (0b01000), 0x0C (0b01100), 0x12 (0b10010), 0x18
(0b11000), 0x1C (0b11100), and 0x1D (0b11101) are capable of accepting a subset of the PCI_SYNC_IN
input frequency range of that of the MPC8240 and thus may not be fully backwards compatible. See
Table 17 for details.
There are two additional reset conguration signals on the MPC8245 which are not used as reset
conguration signals on the MPC8240: SDMA0 and SDMA1.
The SDMA0 reset conguration pin selects between the MPC8245 DUART or the MPC8240 backwards
compatible mode PCI_CLK[0–4] functionality on these multiplexed signals. The default state (logic 1) of
SDMA0 selects the MPC8240 backwards compatible mode of PCI_CLK[0–4] functionality while a logic
0 state on the SDMA0 signal selects DUART functionality. Note if using the DUART mode, four of the
ve PCI clocks, PCI_CLK[0–3], are not available.
The SDMA1 reset conguration pin selects between the MPC8245 Extended ROM functionality or
MPC8240 backwards compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN,
SRESET, TRIG_IN and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backwards compatible mode functionality while a logic 0 state on the SDMA1 signal selects Extended
ROM functionality. Note if using the Extended ROM mode, TBEN, CHKSTOP_IN, SRESET, TRIG_IN
and TRIG_OUT functionality are not available.
The drive capability of the pins for the MPC8245 and that of the MPC8240 vary slightly for the following
driver types: DRV_PCI, DRV_MEM_ADDR, DRV_PCI_CLK, DRV_MEM_DATA. Please refer to the
Drive Capability table in the MPC8240 and the the MPC8245 hardware specications document for more
details.
The programmable PCI output valid and output hold feature controlled by bits in the Power Management
Conguration Register 2 (PMCR2) <0x72> has changed slightly in the MPC8245. For the MPC8240,
three bits, PMCR2[6–4] = PCI_HOLD_DEL, are used to select one of eight possible PCI output timing
congurations. PMCR2[6–5] are software controllable but initially are set by the reset conguration state
of the MCP and CKE signals, respectively; PMCR2[4] can be changed by software. The default
conguration for PMCR2[6–4] = 0b110 since the MCP and CKE signals have internal pull-up resistors,
but this default conguration does not select 33 MHz or 66 MHz PCI operation output timing parameters
for the MPC8240; this choice is made by software. For the MPC8245, only two bits in the Power
Management Conguration Register 2 (PMCR2), PMCR2[5–4] = PCI_HOLD_DEL, control the variable
PCI output timing. PMCR2[5–4] are software controllable but initially are set by the inverted reset
conguration state of the MCP and CKE signals, respectively. The default conguration for
PMCR2[5–4] = 0b00 since the MCP and CKE signals have internal pull-up resistors and the values from
these signals are inverted; this default conguration selects 66 MHz PCI operation output timing
parameters. There are four programmable PCI output timing congurations on the MPC8245, see Table 10
for details.
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