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參數(shù)資料
| 型號： | MPC8245LZU350X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 23/60頁 |
| 文件大?。?/td> | 620K |
| 代理商： | MPC8245LZU350X |
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MPC8245 Integrated Processor Hardware Specications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller, a DUART, I2O controller, and an I
2C controller. The 603e core is a full-featured,
high-performance processor with oating-point support, memory management, 16-Kbyte instruction
cache, 16-Kbyte data cache, and power management features. Integration reduces the overall packaging
requirements and the number of discrete devices required for an embedded system.
The MPC8245 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The 603e core is clocked from a separate PLL, which is referenced to the peripheral
logic PLL. This allows the microprocessor and the peripheral logic block to operate at different
frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus
(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the
interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the
MPC8245 memory space have hardware-invoked memory coherency.
The MPC8245 features serve a variety of embedded applications. In this way, the 603e core and peripheral
logic remain general-purpose. The MPC8245 can be used as either a PCI host or an agent controller.
1.2 Features
Major features of the MPC8245 are as follows:
Processor core
— High-performance, superscalar processor core
— Integer unit (IU), oating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—entire cache or on a per-way basis up to three of four ways
— Dynamic power management—Supports 60x nap, doze, and sleep modes
Peripheral logic
— Peripheral logic bus
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Supports full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Supports up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
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