參數(shù)資料
型號(hào)： MPC823UM_REV1_16-CPM7
廠商： Motorola, Inc.
英文描述： 10 AMP SUBMINIATURE POWER RELAY
中文描述： 通信處理器模塊
文件頁(yè)數(shù)： 69/74頁(yè)
文件大小： 234K
代理商： MPC823UM_REV1_16-CPM7
Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-447
S
C
1
P
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = The TXB or TXE bit in the SPI event register is set when this buffer is serviced. TXB
and TXE can cause interrupts if they are enabled.
L—Last
0 = This buffer does not contain the last character of the message.
1 = This buffer contains the last character of the message.
CM—Continuous Mode
This bit is only valid when the serial peripheral interface is in master mode. In slave mode,
it must be written as a zero.
0 = Normal operation.
1 = The R bit is not cleared by the communication processor module after this buffer
descriptor is closed, thus allowing the associated data buffer to be automatically
retransmitted next time the communication processor module accesses this buffer
descriptor.
UN—Underrun
This bit indicates that the serial peripheral interface has encountered a transmitter underrun
condition while transmitting a data buffer. This error condition is only valid when the serial
peripheral interface is in slave mode. The serial peripheral interface writes this bit after it
finishes transmitting the associated data buffer.
ME—Multimaster Error
This bit indicates that this buffer is closed because the SPISEL pin was asserted when the
serial peripheral interface was in master mode. This indicates a synchronization problem
between multiple masters on the SPI bus. The serial peripheral interface writes this bit after
it finishes transmitting the associated data buffer.
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