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參數(shù)資料
| 型號： | MPC5534MVM80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 51/60頁 |
| 文件大小： | 0K |
| 描述： | MCU 1MB FLASH 80MHZ 208MAPBGA |
| 標準包裝： | 90 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器容量： | 1MB（1M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤 |
| 其它名稱： | Q4437099 T0850514 |
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Revision History for the MPC5534 Data Sheet
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
55
Table 6, VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies
fall outside the operating conditions and until the internal POR asserts.
Subscript all symbol names that appear after the first underscore character.
Removed ‘Tj ‘ after ‘150 C’ in Spec 10, Characteristic column:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies
fall outside the operating conditions and until the internal POR asserts.
Added to Spec 2:
3.3 V (VDDSYN) POR negated (ramp down)
Min 0.0
Max 0.30
V
3.3 V (VDDSYN) POR asserted (ramp up)
Min 0.0
Max 0.30
V
Spec 3: Added new footnote 3 for both lines: ‘It is possible to reach the current limit during ramp up--do not treat
this event as a short circuit current.’
Spec 5: Changed old Footnote 1 (now footnote 2): ‘User must be able to supply full operating current for the 1.5 V
supply when the 3.3 V supply reaches this range.” to ‘Supply full operating current for the 1.5 V supply when the
3.3 V supply reaches this range.”
Specs 7 and 10: added ‘a(chǎn)t Tj ‘ at the end of the first line in the second column: Characteristic.
Spec 10:
Added cross-reference to footnote 6: ‘IVRCCTL is measured at the following conditions: VDD = 1.35 V,
VRC33 = 3.1 V, VVRCCTL = 2.2 V.’ Changed ‘(@ VDD = 1.35 V, fsys = fMAX)‘ to ‘(@ fsys = fMAX).
Added old footnote 5 new footnote 6.
Added a new footnote 7, ‘Refer to Table 1 for the maximum operating frequency.’
Rewrote old footnote 8 (new footnote 9) to: Represents the worst-case external transistor BETA. It is measured
on a per part basis and calculated as (IDD IVRCCTL).
Deleted footnote 9 Preliminary value, Final specification pending characterization.
Table 7, Power Sequence Pin Status for Fast Pads: Changed title to Pin Status for Fast Pads During the Power Sequence
Table 8, Power Sequence Pin Status for Medium/Slow Pads:
Changed title to Pin Status for Medium and Slow Pads During the Power Sequence
Updated preceding paragraph.
Table 9, DC Electrical Specifications:
Spelled out meaning of the slash ‘/’ as ‘a(chǎn)nd’. Still confusing. Deleted ‘I/O’ from the specs to improve clarity.
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if EBTS = 0; VDDE2 and VDDE3 have
a range of 1.6–3.6 V if EBTS =1.
Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (IOH_S = –2.0 mA):’
Created a left-justified second line and moved ‘IOH_S = –2.0 mA’ from the 1st line to the second line and deleted
the parentheses. Created a left-justified third line that reads ‘IOH_S = –1.0 mA.’
Spec 20, column 4, Min: Added a blank line before and after ‘0.80
V
DDEH’ and put ‘0.85 VDDEH’ on the last line.
Spec 22, column 2, ’Slow and medium output low voltage (IOL_S = 2.0 mA):’ Created a left-justified second line
and moved ‘IOL_S = 2.0 mA.’ from the 1st line to the second line and deleted the parentheses. Created a
left-justified third line that reads ‘IOL_S = 1.0 mA.’
Spec 22, column 5, Max: Added a blank line before and after ‘0.20
V
DDEH’ and put ‘0.15 VDDEH’ on the last
line.
Spec 26: Changed ‘AN[12]_MA[1]_SDO’ to ‘AN[13]_MA[1]_SDO’.
Spec 28: Changed 82 MHz to fMAX MHz.
Footnote 9: Changed from ‘Preliminary. Final specification pending characterization.’ to ‘ shows an illustration of
the IDD_STBY values interpolated for these temperature values.’
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
Location
Description of Changes
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